Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99919065	1			T1	159217		T2	304		T3	210174
all_values[1]	99919065	1			T1	159217		T2	304		T3	210174
all_values[2]	99919065	1			T1	159217		T2	304		T3	210174

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

498808

1

T1

25

T3

9

T33

7

auto[1]

299258387

1

T1

477626

T2

912

T3

630513

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298239510

1

T1

476283

T2

876

T3

628761

auto[1]

1517685

1

T1

1368

T2

36

T3

1761

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	145216	1			T3	1		T7	56		T9	583
all_values[0]	auto[0]	auto[1]	1918	1			T3	2		T7	2		T9	8
all_values[0]	auto[1]	auto[0]	99267954	1			T1	158761		T2	292		T3	209586
all_values[0]	auto[1]	auto[1]	503977	1			T1	456		T2	12		T3	585
all_values[1]	auto[0]	auto[0]	179375	1			T1	17		T3	1		T33	5
all_values[1]	auto[0]	auto[1]	1509	1			T1	8		T3	2		T33	2
all_values[1]	auto[1]	auto[0]	99233795	1			T1	158744		T2	292		T3	209586
all_values[1]	auto[1]	auto[1]	504386	1			T1	448		T2	12		T3	585
all_values[2]	auto[0]	auto[0]	169301	1			T3	1		T12	21		T7	56
all_values[2]	auto[0]	auto[1]	1489	1			T3	2		T7	2		T8	1
all_values[2]	auto[1]	auto[0]	99243869	1			T1	158761		T2	292		T3	209586
all_values[2]	auto[1]	auto[1]	504406	1			T1	456		T2	12		T3	585