Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
372020 |
1 |
|
|
T1 |
620 |
|
T2 |
18 |
|
T3 |
2 |
auto[1] |
315834 |
1 |
|
|
T3 |
746 |
|
T34 |
4528 |
|
T35 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172937 |
1 |
|
|
T1 |
152 |
|
T3 |
178 |
|
T32 |
197 |
lower_val |
170893 |
1 |
|
|
T1 |
159 |
|
T2 |
11 |
|
T3 |
186 |
zero_val |
1818 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
264196 |
1 |
|
|
T1 |
304 |
|
T2 |
12 |
|
T3 |
218 |
lower_val |
264302 |
1 |
|
|
T1 |
316 |
|
T2 |
6 |
|
T3 |
162 |
zero_val |
159356 |
1 |
|
|
T3 |
368 |
|
T34 |
2250 |
|
T35 |
384 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46661 |
1 |
|
|
T1 |
67 |
|
T32 |
111 |
|
T33 |
91 |
higher_val |
higher_val |
auto[1] |
19730 |
1 |
|
|
T3 |
45 |
|
T34 |
304 |
|
T35 |
52 |
higher_val |
lower_val |
auto[0] |
46587 |
1 |
|
|
T1 |
85 |
|
T32 |
86 |
|
T33 |
89 |
higher_val |
lower_val |
auto[1] |
19782 |
1 |
|
|
T3 |
40 |
|
T34 |
276 |
|
T35 |
42 |
higher_val |
zero_val |
auto[0] |
74 |
1 |
|
|
T35 |
1 |
|
T39 |
1 |
|
T13 |
1 |
higher_val |
zero_val |
auto[1] |
40103 |
1 |
|
|
T3 |
93 |
|
T34 |
570 |
|
T35 |
88 |
lower_val |
higher_val |
auto[0] |
46364 |
1 |
|
|
T1 |
89 |
|
T2 |
8 |
|
T32 |
89 |
lower_val |
higher_val |
auto[1] |
19461 |
1 |
|
|
T3 |
48 |
|
T34 |
288 |
|
T35 |
45 |
lower_val |
lower_val |
auto[0] |
46055 |
1 |
|
|
T1 |
70 |
|
T2 |
3 |
|
T32 |
97 |
lower_val |
lower_val |
auto[1] |
19422 |
1 |
|
|
T3 |
45 |
|
T34 |
291 |
|
T35 |
34 |
lower_val |
zero_val |
auto[0] |
95 |
1 |
|
|
T7 |
1 |
|
T189 |
1 |
|
T103 |
1 |
lower_val |
zero_val |
auto[1] |
39496 |
1 |
|
|
T3 |
93 |
|
T34 |
579 |
|
T35 |
81 |
zero_val |
higher_val |
auto[0] |
571 |
1 |
|
|
T1 |
1 |
|
T34 |
1 |
|
T8 |
1 |
zero_val |
higher_val |
auto[1] |
118 |
1 |
|
|
T9 |
2 |
|
T74 |
1 |
|
T190 |
1 |
zero_val |
lower_val |
auto[0] |
569 |
1 |
|
|
T2 |
1 |
|
T32 |
1 |
|
T33 |
1 |
zero_val |
lower_val |
auto[1] |
110 |
1 |
|
|
T34 |
2 |
|
T9 |
1 |
|
T74 |
1 |
zero_val |
zero_val |
auto[0] |
268 |
1 |
|
|
T3 |
1 |
|
T35 |
1 |
|
T7 |
1 |
zero_val |
zero_val |
auto[1] |
182 |
1 |
|
|
T34 |
2 |
|
T9 |
1 |
|
T74 |
6 |