Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10267	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8855	1			T1	24		T3	19		T32	17
len_5001_7500	14142	1			T1	24		T3	18		T32	17
len_2501_5000	9173	1			T1	24		T3	18		T32	17
len_1025_2500	5402	1			T1	14		T3	11		T32	10
len_769_1024	6216	1			T1	2		T3	2		T32	2
len_513_768	6696	1			T1	3		T3	2		T32	2
len_257_512	20938	1			T1	2		T3	2		T32	2
len_0_256	255479	1			T1	211		T2	9		T3	274
len_keccak_block_sizes[72]	712	1			T1	2		T3	2		T32	2
len_keccak_block_sizes[104]	624	1			T1	2		T3	2		T32	2
len_keccak_block_sizes[136]	519	1			T3	2		T32	2		T33	2
len_keccak_block_sizes[144]	418	1			T32	2		T33	2		T34	3
len_keccak_block_sizes[168]	317	1			T34	3		T74	3		T191	3
len_1	742	1			T1	2		T3	2		T32	2
len_0	1175	1			T1	2		T3	2		T32	2