Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99919065	1			T1	159217		T2	304		T3	210174
all_pins[1]	99919065	1			T1	159217		T2	304		T3	210174
all_pins[2]	99919065	1			T1	159217		T2	304		T3	210174

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298977157	1			T1	477195		T2	900		T3	629937
values[0x1]	780038	1			T1	456		T2	12		T3	585
transitions[0x0=>0x1]	778217	1			T1	456		T2	12		T3	585
transitions[0x1=>0x0]	778237	1			T1	456		T2	12		T3	585

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99415088	1			T1	158761		T2	292		T3	209589
all_pins[0]	values[0x1]	503977	1			T1	456		T2	12		T3	585
all_pins[0]	transitions[0x0=>0x1]	503959	1			T1	456		T2	12		T3	585
all_pins[0]	transitions[0x1=>0x0]	5110	1			T9	1		T37	72		T40	11
all_pins[1]	values[0x0]	99913937	1			T1	159217		T2	304		T3	210174
all_pins[1]	values[0x1]	5128	1			T9	1		T37	72		T40	11
all_pins[1]	transitions[0x0=>0x1]	4906	1			T9	1		T37	72		T40	11
all_pins[1]	transitions[0x1=>0x0]	270711	1			T8	556		T41	750		T23	406
all_pins[2]	values[0x0]	99648132	1			T1	159217		T2	304		T3	210174
all_pins[2]	values[0x1]	270933	1			T8	556		T41	750		T23	406
all_pins[2]	transitions[0x0=>0x1]	269352	1			T8	556		T41	750		T23	406
all_pins[2]	transitions[0x1=>0x0]	502416	1			T1	456		T2	12		T3	585