Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10597611 |
1 |
|
|
T1 |
3720 |
|
T2 |
96 |
|
T3 |
2992 |
auto[1] |
10597538 |
1 |
|
|
T1 |
3720 |
|
T2 |
96 |
|
T3 |
2992 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20959221 |
1 |
|
|
T1 |
7440 |
|
T2 |
192 |
|
T3 |
5984 |
triple_byte_access |
78480 |
1 |
|
|
T34 |
620 |
|
T7 |
42 |
|
T8 |
40 |
halfword_access |
78830 |
1 |
|
|
T34 |
632 |
|
T7 |
52 |
|
T8 |
28 |
byte_access |
78618 |
1 |
|
|
T34 |
620 |
|
T7 |
44 |
|
T8 |
46 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10479647 |
1 |
|
|
T1 |
3720 |
|
T2 |
96 |
|
T3 |
2992 |
auto[0] |
triple_byte_access |
39240 |
1 |
|
|
T34 |
310 |
|
T7 |
21 |
|
T8 |
20 |
auto[0] |
halfword_access |
39415 |
1 |
|
|
T34 |
316 |
|
T7 |
26 |
|
T8 |
14 |
auto[0] |
byte_access |
39309 |
1 |
|
|
T34 |
310 |
|
T7 |
22 |
|
T8 |
23 |
auto[1] |
word_access |
10479574 |
1 |
|
|
T1 |
3720 |
|
T2 |
96 |
|
T3 |
2992 |
auto[1] |
triple_byte_access |
39240 |
1 |
|
|
T34 |
310 |
|
T7 |
21 |
|
T8 |
20 |
auto[1] |
halfword_access |
39415 |
1 |
|
|
T34 |
316 |
|
T7 |
26 |
|
T8 |
14 |
auto[1] |
byte_access |
39309 |
1 |
|
|
T34 |
310 |
|
T7 |
22 |
|
T8 |
23 |