Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100484964	1			T1	13941		T2	80947		T3	2524
all_values[1]	100484964	1			T1	13941		T2	80947		T3	2524
all_values[2]	100484964	1			T1	13941		T2	80947		T3	2524

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

466027

1

T1

97

T2

6747

T3

18

auto[1]

300988865

1

T1

41726

T2

236094

T3

7554

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299938104

1

T1

41412

T2

242118

T3

6918

auto[1]

1516788

1

T1

411

T2

723

T3

654

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	140294	1			T2	245		T33	3		T17	223
all_values[0]	auto[0]	auto[1]	1792	1			T2	4		T33	2		T17	2
all_values[0]	auto[1]	auto[0]	99839074	1			T1	13804		T2	80461		T3	2306
all_values[0]	auto[1]	auto[1]	503804	1			T1	137		T2	237		T3	218
all_values[1]	auto[0]	auto[0]	153143	1			T2	3410		T3	16		T34	5
all_values[1]	auto[0]	auto[1]	1387	1			T2	2		T3	2		T34	1
all_values[1]	auto[1]	auto[0]	99826225	1			T1	13804		T2	77296		T3	2290
all_values[1]	auto[1]	auto[1]	504209	1			T1	137		T2	239		T3	216
all_values[2]	auto[0]	auto[0]	167965	1			T1	95		T2	3084		T33	29
all_values[2]	auto[0]	auto[1]	1446	1			T1	2		T2	2		T33	7
all_values[2]	auto[1]	auto[0]	99811403	1			T1	13709		T2	77622		T3	2306
all_values[2]	auto[1]	auto[1]	504150	1			T1	135		T2	239		T3	218