Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100484964	1			T1	13941		T2	80947		T3	2524
all_pins[1]	100484964	1			T1	13941		T2	80947		T3	2524
all_pins[2]	100484964	1			T1	13941		T2	80947		T3	2524

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300657614	1			T1	41686		T2	242604		T3	7354
values[0x1]	797278	1			T1	137		T2	237		T3	218
transitions[0x0=>0x1]	795210	1			T1	137		T2	237		T3	218
transitions[0x1=>0x0]	795235	1			T1	137		T2	237		T3	218

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99981160	1			T1	13804		T2	80710		T3	2306
all_pins[0]	values[0x1]	503804	1			T1	137		T2	237		T3	218
all_pins[0]	transitions[0x0=>0x1]	503789	1			T1	137		T2	237		T3	218
all_pins[0]	transitions[0x1=>0x0]	6050	1			T45	2		T38	32		T143	23
all_pins[1]	values[0x0]	100478899	1			T1	13941		T2	80947		T3	2524
all_pins[1]	values[0x1]	6065	1			T45	2		T38	32		T143	23
all_pins[1]	transitions[0x0=>0x1]	5729	1			T45	2		T38	32		T143	23
all_pins[1]	transitions[0x1=>0x0]	287073	1			T7	199		T19	848		T14	7345
all_pins[2]	values[0x0]	100197555	1			T1	13941		T2	80947		T3	2524
all_pins[2]	values[0x1]	287409	1			T7	199		T19	848		T14	7345
all_pins[2]	transitions[0x0=>0x1]	285692	1			T7	198		T19	848		T14	7297
all_pins[2]	transitions[0x1=>0x0]	502112	1			T1	137		T2	237		T3	218