Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10609603 |
1 |
|
|
T1 |
17199 |
|
T2 |
23260 |
|
T3 |
25111 |
auto[1] |
10609540 |
1 |
|
|
T1 |
17199 |
|
T2 |
23260 |
|
T3 |
25111 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20982851 |
1 |
|
|
T1 |
34262 |
|
T2 |
46294 |
|
T3 |
49984 |
triple_byte_access |
78582 |
1 |
|
|
T1 |
42 |
|
T2 |
60 |
|
T3 |
60 |
halfword_access |
79150 |
1 |
|
|
T1 |
52 |
|
T2 |
84 |
|
T3 |
82 |
byte_access |
78560 |
1 |
|
|
T1 |
42 |
|
T2 |
82 |
|
T3 |
96 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10491457 |
1 |
|
|
T1 |
17131 |
|
T2 |
23147 |
|
T3 |
24992 |
auto[0] |
triple_byte_access |
39291 |
1 |
|
|
T1 |
21 |
|
T2 |
30 |
|
T3 |
30 |
auto[0] |
halfword_access |
39575 |
1 |
|
|
T1 |
26 |
|
T2 |
42 |
|
T3 |
41 |
auto[0] |
byte_access |
39280 |
1 |
|
|
T1 |
21 |
|
T2 |
41 |
|
T3 |
48 |
auto[1] |
word_access |
10491394 |
1 |
|
|
T1 |
17131 |
|
T2 |
23147 |
|
T3 |
24992 |
auto[1] |
triple_byte_access |
39291 |
1 |
|
|
T1 |
21 |
|
T2 |
30 |
|
T3 |
30 |
auto[1] |
halfword_access |
39575 |
1 |
|
|
T1 |
26 |
|
T2 |
42 |
|
T3 |
41 |
auto[1] |
byte_access |
39280 |
1 |
|
|
T1 |
21 |
|
T2 |
41 |
|
T3 |
48 |