Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99860239	1			T1	1053		T2	1552		T7	52426
all_values[1]	99860239	1			T1	1053		T2	1552		T7	52426
all_values[2]	99860239	1			T1	1053		T2	1552		T7	52426

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

511437

1

T1

384

T2

58

T7

4052

auto[1]

299069280

1

T1

2775

T2

4598

T7

153226

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298066353

1

T1

3141

T2

4182

T7

156939

auto[1]

1514364

1

T1

18

T2

474

T7

339

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	203211	1			T2	47		T7	1983		T8	491
all_values[0]	auto[0]	auto[1]	2081	1			T2	6		T7	6		T8	16
all_values[0]	auto[1]	auto[0]	99152240	1			T1	1047		T2	1347		T7	50330
all_values[0]	auto[1]	auto[1]	502707	1			T1	6		T2	152		T7	107
all_values[1]	auto[0]	auto[0]	163641	1			T1	381		T7	71		T8	591
all_values[1]	auto[0]	auto[1]	1532	1			T1	3		T7	3		T8	8
all_values[1]	auto[1]	auto[0]	99191810	1			T1	666		T2	1394		T7	52242
all_values[1]	auto[1]	auto[1]	503256	1			T1	3		T2	158		T7	110
all_values[2]	auto[0]	auto[0]	139447	1			T2	3		T7	1984		T8	261
all_values[2]	auto[0]	auto[1]	1525	1			T2	2		T7	5		T8	6
all_values[2]	auto[1]	auto[0]	99216004	1			T1	1047		T2	1391		T7	50329
all_values[2]	auto[1]	auto[1]	503263	1			T1	6		T2	156		T7	108