Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
364860 |
1 |
|
|
T1 |
12 |
|
T2 |
206 |
|
T7 |
76 |
auto[1] |
320032 |
1 |
|
|
T7 |
96 |
|
T8 |
220 |
|
T36 |
144 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
170799 |
1 |
|
|
T1 |
2 |
|
T2 |
36 |
|
T7 |
40 |
lower_val |
169666 |
1 |
|
|
T1 |
3 |
|
T2 |
50 |
|
T7 |
51 |
zero_val |
1770 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
262128 |
1 |
|
|
T1 |
4 |
|
T2 |
116 |
|
T7 |
66 |
lower_val |
262040 |
1 |
|
|
T1 |
8 |
|
T2 |
90 |
|
T7 |
60 |
zero_val |
160724 |
1 |
|
|
T7 |
46 |
|
T8 |
112 |
|
T36 |
74 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45255 |
1 |
|
|
T2 |
21 |
|
T7 |
10 |
|
T8 |
33 |
higher_val |
higher_val |
auto[1] |
20086 |
1 |
|
|
T7 |
7 |
|
T8 |
12 |
|
T36 |
11 |
higher_val |
lower_val |
auto[0] |
45604 |
1 |
|
|
T1 |
2 |
|
T2 |
15 |
|
T7 |
12 |
higher_val |
lower_val |
auto[1] |
20065 |
1 |
|
|
T7 |
5 |
|
T8 |
12 |
|
T36 |
7 |
higher_val |
zero_val |
auto[0] |
64 |
1 |
|
|
T8 |
1 |
|
T76 |
1 |
|
T41 |
1 |
higher_val |
zero_val |
auto[1] |
39725 |
1 |
|
|
T7 |
6 |
|
T8 |
26 |
|
T36 |
12 |
lower_val |
higher_val |
auto[0] |
45107 |
1 |
|
|
T1 |
2 |
|
T2 |
33 |
|
T7 |
12 |
lower_val |
higher_val |
auto[1] |
19949 |
1 |
|
|
T7 |
9 |
|
T8 |
20 |
|
T36 |
11 |
lower_val |
lower_val |
auto[0] |
44916 |
1 |
|
|
T1 |
1 |
|
T2 |
17 |
|
T7 |
9 |
lower_val |
lower_val |
auto[1] |
19833 |
1 |
|
|
T7 |
5 |
|
T8 |
10 |
|
T36 |
9 |
lower_val |
zero_val |
auto[0] |
67 |
1 |
|
|
T8 |
1 |
|
T187 |
1 |
|
T188 |
1 |
lower_val |
zero_val |
auto[1] |
39794 |
1 |
|
|
T7 |
16 |
|
T8 |
34 |
|
T36 |
22 |
zero_val |
higher_val |
auto[0] |
546 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T17 |
1 |
zero_val |
higher_val |
auto[1] |
121 |
1 |
|
|
T7 |
1 |
|
T8 |
1 |
|
T14 |
2 |
zero_val |
lower_val |
auto[0] |
553 |
1 |
|
|
T1 |
1 |
|
T8 |
2 |
|
T33 |
1 |
zero_val |
lower_val |
auto[1] |
111 |
1 |
|
|
T8 |
1 |
|
T14 |
1 |
|
T41 |
1 |
zero_val |
zero_val |
auto[0] |
227 |
1 |
|
|
T36 |
1 |
|
T64 |
1 |
|
T76 |
1 |
zero_val |
zero_val |
auto[1] |
212 |
1 |
|
|
T7 |
1 |
|
T8 |
1 |
|
T14 |
1 |