Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99860239	1			T1	1053		T2	1552		T7	52426
all_pins[1]	99860239	1			T1	1053		T2	1552		T7	52426
all_pins[2]	99860239	1			T1	1053		T2	1552		T7	52426

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298805726	1			T1	3153		T2	4482		T7	157141
values[0x1]	774991	1			T1	6		T2	174		T7	137
transitions[0x0=>0x1]	773100	1			T1	6		T2	174		T7	137
transitions[0x1=>0x0]	773128	1			T1	6		T2	174		T7	137

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99357532	1			T1	1047		T2	1400		T7	52319
all_pins[0]	values[0x1]	502707	1			T1	6		T2	152		T7	107
all_pins[0]	transitions[0x0=>0x1]	502696	1			T1	6		T2	152		T7	107
all_pins[0]	transitions[0x1=>0x0]	5634	1			T2	22		T7	30		T14	65
all_pins[1]	values[0x0]	99854594	1			T1	1053		T2	1530		T7	52396
all_pins[1]	values[0x1]	5645	1			T2	22		T7	30		T14	65
all_pins[1]	transitions[0x0=>0x1]	5400	1			T2	22		T7	30		T14	64
all_pins[1]	transitions[0x1=>0x0]	266394	1			T14	696		T15	9347		T16	4856
all_pins[2]	values[0x0]	99593600	1			T1	1053		T2	1552		T7	52426
all_pins[2]	values[0x1]	266639	1			T14	697		T15	9347		T16	4856
all_pins[2]	transitions[0x0=>0x1]	265004	1			T14	694		T15	9276		T16	4825
all_pins[2]	transitions[0x1=>0x0]	501100	1			T1	6		T2	152		T7	107