Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	614	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5292	1			T2	11		T7	8		T8	31
len_601_800	11628	1			T1	2		T2	49		T7	26
len_401_600	7597	1			T1	1		T2	17		T7	13
len_201_400	16243	1			T2	17		T7	8		T8	10
len_65_200	73256	1			T2	7		T7	5		T8	9
len_min_for_xof_require_squeeze	987	1			T8	1		T33	10		T19	1
len_keccak_block_sizes[72]	751	1			T33	5		T14	1		T99	1
len_keccak_block_sizes[104]	742	1			T33	5		T189	1		T190	1
len_keccak_block_sizes[136]	762	1			T33	5		T35	1		T14	1
len_keccak_block_sizes[144]	278	1			T33	5		T14	1		T37	1
len_keccak_block_sizes[168]	275	1			T33	5		T78	1		T191	5
len_datapath_width	13931	1			T1	1		T7	1		T8	4
len_2_63	212449	1			T1	1		T2	1		T7	20
len_1	38	1			T8	1		T192	1		T149	1