Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336000 |
1 |
|
|
T1 |
6 |
|
T2 |
102 |
|
T7 |
90 |
auto[1] |
2918 |
1 |
|
|
T1 |
1 |
|
T7 |
7 |
|
T8 |
14 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
304987 |
1 |
|
|
T1 |
2 |
|
T2 |
24 |
|
T7 |
32 |
auto[1] |
33931 |
1 |
|
|
T1 |
5 |
|
T2 |
78 |
|
T7 |
65 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326307 |
1 |
|
|
T1 |
3 |
|
T2 |
102 |
|
T7 |
80 |
auto[1] |
12611 |
1 |
|
|
T1 |
4 |
|
T7 |
17 |
|
T8 |
28 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
12611 |
1 |
|
|
T1 |
4 |
|
T7 |
17 |
|
T8 |
28 |
sw_kmac_invalid_sideload |
326307 |
1 |
|
|
T1 |
3 |
|
T2 |
102 |
|
T7 |
80 |
app_valid_sideload |
12611 |
1 |
|
|
T1 |
4 |
|
T7 |
17 |
|
T8 |
28 |
app_invalid_sideload |
326307 |
1 |
|
|
T1 |
3 |
|
T2 |
102 |
|
T7 |
80 |