Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10288162 |
1 |
|
|
T1 |
640 |
|
T2 |
16863 |
|
T7 |
12158 |
auto[1] |
10288143 |
1 |
|
|
T1 |
640 |
|
T2 |
16863 |
|
T7 |
12158 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20342395 |
1 |
|
|
T1 |
1274 |
|
T2 |
33564 |
|
T7 |
24206 |
triple_byte_access |
77876 |
1 |
|
|
T2 |
68 |
|
T7 |
40 |
|
T8 |
76 |
halfword_access |
78312 |
1 |
|
|
T1 |
2 |
|
T2 |
40 |
|
T7 |
38 |
byte_access |
77722 |
1 |
|
|
T1 |
4 |
|
T2 |
54 |
|
T7 |
32 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10171207 |
1 |
|
|
T1 |
637 |
|
T2 |
16782 |
|
T7 |
12103 |
auto[0] |
triple_byte_access |
38938 |
1 |
|
|
T2 |
34 |
|
T7 |
20 |
|
T8 |
38 |
auto[0] |
halfword_access |
39156 |
1 |
|
|
T1 |
1 |
|
T2 |
20 |
|
T7 |
19 |
auto[0] |
byte_access |
38861 |
1 |
|
|
T1 |
2 |
|
T2 |
27 |
|
T7 |
16 |
auto[1] |
word_access |
10171188 |
1 |
|
|
T1 |
637 |
|
T2 |
16782 |
|
T7 |
12103 |
auto[1] |
triple_byte_access |
38938 |
1 |
|
|
T2 |
34 |
|
T7 |
20 |
|
T8 |
38 |
auto[1] |
halfword_access |
39156 |
1 |
|
|
T1 |
1 |
|
T2 |
20 |
|
T7 |
19 |
auto[1] |
byte_access |
38861 |
1 |
|
|
T1 |
2 |
|
T2 |
27 |
|
T7 |
16 |