Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99666729	1			T1	26104		T2	263075		T3	158418
all_values[1]	99666729	1			T1	26104		T2	263075		T3	158418
all_values[2]	99666729	1			T1	26104		T2	263075		T3	158418

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

463426

1

T1

379

T2

6157

T3

6

auto[1]

298536761

1

T1

77933

T2

783068

T3

475248

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297493101

1

T1

77631

T2

788505

T3

473844

auto[1]

1507086

1

T1

681

T2

720

T3

1410

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	157057	1			T3	1		T38	1		T39	3
all_values[0]	auto[0]	auto[1]	1911	1			T3	2		T38	2		T39	4
all_values[0]	auto[1]	auto[0]	99007310	1			T1	25877		T2	262835		T3	157947
all_values[0]	auto[1]	auto[1]	500451	1			T1	227		T2	240		T3	468
all_values[1]	auto[0]	auto[0]	154733	1			T1	316		T3	1		T7	236
all_values[1]	auto[0]	auto[1]	1509	1			T1	3		T3	2		T7	2
all_values[1]	auto[1]	auto[0]	99009634	1			T1	25561		T2	262835		T3	157947
all_values[1]	auto[1]	auto[1]	500853	1			T1	224		T2	240		T3	468
all_values[2]	auto[0]	auto[0]	146766	1			T1	59		T2	6152		T38	1
all_values[2]	auto[0]	auto[1]	1450	1			T1	1		T2	5		T38	2
all_values[2]	auto[1]	auto[0]	99017601	1			T1	25818		T2	256683		T3	157948
all_values[2]	auto[1]	auto[1]	500912	1			T1	226		T2	235		T3	470