Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
351000 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T2 | 
2 | 
 | 
T3 | 
2 | 
| auto[1] | 
330734 | 
1 | 
 | 
 | 
T1 | 
346 | 
 | 
T2 | 
330 | 
 | 
T3 | 
618 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
170600 | 
1 | 
 | 
 | 
T1 | 
106 | 
 | 
T2 | 
84 | 
 | 
T3 | 
160 | 
| lower_val | 
168521 | 
1 | 
 | 
 | 
T1 | 
84 | 
 | 
T2 | 
68 | 
 | 
T3 | 
156 | 
| zero_val | 
1726 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
3 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
258544 | 
1 | 
 | 
 | 
T1 | 
106 | 
 | 
T2 | 
86 | 
 | 
T3 | 
146 | 
| lower_val | 
257664 | 
1 | 
 | 
 | 
T1 | 
82 | 
 | 
T2 | 
100 | 
 | 
T3 | 
130 | 
| zero_val | 
165526 | 
1 | 
 | 
 | 
T1 | 
160 | 
 | 
T2 | 
146 | 
 | 
T3 | 
344 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
18 | 
0 | 
18 | 
100.00 | 
 | 
Automatically Generated Cross Bins for entropy_timer_cross
Bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
higher_val | 
auto[0] | 
44083 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T7 | 
20 | 
 | 
T40 | 
3 | 
| higher_val | 
higher_val | 
auto[1] | 
20688 | 
1 | 
 | 
 | 
T1 | 
33 | 
 | 
T2 | 
23 | 
 | 
T3 | 
42 | 
| higher_val | 
lower_val | 
auto[0] | 
43996 | 
1 | 
 | 
 | 
T7 | 
17 | 
 | 
T40 | 
2 | 
 | 
T8 | 
44 | 
| higher_val | 
lower_val | 
auto[1] | 
20671 | 
1 | 
 | 
 | 
T1 | 
28 | 
 | 
T2 | 
23 | 
 | 
T3 | 
32 | 
| higher_val | 
zero_val | 
auto[0] | 
71 | 
1 | 
 | 
 | 
T94 | 
1 | 
 | 
T73 | 
1 | 
 | 
T199 | 
1 | 
| higher_val | 
zero_val | 
auto[1] | 
41091 | 
1 | 
 | 
 | 
T1 | 
45 | 
 | 
T2 | 
38 | 
 | 
T3 | 
85 | 
| lower_val | 
higher_val | 
auto[0] | 
43383 | 
1 | 
 | 
 | 
T7 | 
17 | 
 | 
T40 | 
1 | 
 | 
T8 | 
49 | 
| lower_val | 
higher_val | 
auto[1] | 
20490 | 
1 | 
 | 
 | 
T1 | 
22 | 
 | 
T2 | 
19 | 
 | 
T3 | 
40 | 
| lower_val | 
lower_val | 
auto[0] | 
43106 | 
1 | 
 | 
 | 
T7 | 
21 | 
 | 
T40 | 
1 | 
 | 
T8 | 
38 | 
| lower_val | 
lower_val | 
auto[1] | 
20471 | 
1 | 
 | 
 | 
T1 | 
20 | 
 | 
T2 | 
18 | 
 | 
T3 | 
35 | 
| lower_val | 
zero_val | 
auto[0] | 
88 | 
1 | 
 | 
 | 
T39 | 
1 | 
 | 
T76 | 
1 | 
 | 
T77 | 
1 | 
| lower_val | 
zero_val | 
auto[1] | 
40983 | 
1 | 
 | 
 | 
T1 | 
42 | 
 | 
T2 | 
31 | 
 | 
T3 | 
81 | 
| zero_val | 
higher_val | 
auto[0] | 
544 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T45 | 
1 | 
 | 
T200 | 
1 | 
| zero_val | 
higher_val | 
auto[1] | 
114 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T94 | 
4 | 
 | 
T201 | 
1 | 
| zero_val | 
lower_val | 
auto[0] | 
539 | 
1 | 
 | 
 | 
T7 | 
1 | 
 | 
T40 | 
1 | 
 | 
T8 | 
1 | 
| zero_val | 
lower_val | 
auto[1] | 
118 | 
1 | 
 | 
 | 
T56 | 
2 | 
 | 
T94 | 
7 | 
 | 
T16 | 
2 | 
| zero_val | 
zero_val | 
auto[0] | 
249 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T38 | 
1 | 
| zero_val | 
zero_val | 
auto[1] | 
162 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T39 | 
2 | 
 | 
T56 | 
2 |