Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10296	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8885	1			T2	29		T3	24		T39	19
len_5001_7500	14125	1			T2	90		T3	24		T38	33
len_2501_5000	9166	1			T2	23		T3	24		T38	34
len_1025_2500	5334	1			T2	6		T3	14		T38	20
len_769_1024	5717	1			T1	46		T2	1		T3	2
len_513_768	6082	1			T1	35		T3	3		T7	6
len_257_512	20383	1			T1	48		T2	1		T3	2
len_0_256	254584	1			T1	28		T2	16		T3	211
len_keccak_block_sizes[72]	723	1			T3	2		T38	2		T39	2
len_keccak_block_sizes[104]	614	1			T3	2		T39	2		T8	1
len_keccak_block_sizes[136]	518	1			T39	2		T56	3		T94	3
len_keccak_block_sizes[144]	417	1			T56	3		T94	3		T162	2
len_keccak_block_sizes[168]	320	1			T56	3		T94	3		T163	3
len_1	761	1			T3	2		T38	2		T39	2
len_0	1173	1			T2	4		T3	2		T38	2