Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99666729	1			T1	26104		T2	263075		T3	158418
all_pins[1]	99666729	1			T1	26104		T2	263075		T3	158418
all_pins[2]	99666729	1			T1	26104		T2	263075		T3	158418

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298240450	1			T1	77002		T2	788907		T3	474786
values[0x1]	759737	1			T1	1310		T2	318		T3	468
transitions[0x0=>0x1]	757975	1			T1	1310		T2	318		T3	468
transitions[0x1=>0x0]	757994	1			T1	1310		T2	318		T3	468

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99166278	1			T1	25877		T2	262835		T3	157950
all_pins[0]	values[0x1]	500451	1			T1	227		T2	240		T3	468
all_pins[0]	transitions[0x0=>0x1]	500442	1			T1	227		T2	240		T3	468
all_pins[0]	transitions[0x1=>0x0]	5909	1			T2	78		T7	6		T8	50
all_pins[1]	values[0x0]	99660811	1			T1	26104		T2	262997		T3	158418
all_pins[1]	values[0x1]	5918	1			T2	78		T7	6		T8	50
all_pins[1]	transitions[0x0=>0x1]	5703	1			T2	78		T7	6		T8	50
all_pins[1]	transitions[0x1=>0x0]	253153	1			T1	1083		T22	399		T15	3576
all_pins[2]	values[0x0]	99413361	1			T1	25021		T2	263075		T3	158418
all_pins[2]	values[0x1]	253368	1			T1	1083		T22	399		T15	3576
all_pins[2]	transitions[0x0=>0x1]	251830	1			T1	1083		T22	399		T15	3547
all_pins[2]	transitions[0x1=>0x0]	498932	1			T1	227		T2	240		T3	468