Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	596	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5085	1			T1	24		T2	29		T7	7
len_601_800	11418	1			T1	43		T2	54		T7	19
len_401_600	7686	1			T1	34		T2	41		T7	9
len_201_400	15991	1			T1	16		T2	14		T7	5
len_65_200	72931	1			T1	6		T2	15		T7	2
len_min_for_xof_require_squeeze	980	1			T56	9		T94	9		T22	1
len_keccak_block_sizes[72]	740	1			T56	9		T94	9		T166	1
len_keccak_block_sizes[104]	748	1			T56	9		T94	9		T166	2
len_keccak_block_sizes[136]	750	1			T56	9		T94	9		T55	1
len_keccak_block_sizes[144]	281	1			T166	1		T77	1		T163	5
len_keccak_block_sizes[168]	281	1			T77	1		T163	5		T16	1
len_datapath_width	13777	1			T1	1		T38	246		T40	3
len_2_63	212022	1			T1	9		T2	10		T3	310
len_1	59	1			T166	1		T77	1		T16	1