Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
334291 |
1 |
|
|
T1 |
176 |
|
T2 |
161 |
|
T3 |
301 |
auto[1] |
3084 |
1 |
|
|
T1 |
2 |
|
T7 |
15 |
|
T4 |
1 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
302595 |
1 |
|
|
T1 |
50 |
|
T2 |
33 |
|
T3 |
301 |
auto[1] |
34780 |
1 |
|
|
T1 |
128 |
|
T2 |
128 |
|
T7 |
44 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
324598 |
1 |
|
|
T1 |
151 |
|
T2 |
161 |
|
T3 |
301 |
auto[1] |
12777 |
1 |
|
|
T1 |
27 |
|
T7 |
28 |
|
T4 |
1 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
12777 |
1 |
|
|
T1 |
27 |
|
T7 |
28 |
|
T4 |
1 |
sw_kmac_invalid_sideload |
324598 |
1 |
|
|
T1 |
151 |
|
T2 |
161 |
|
T3 |
301 |
app_valid_sideload |
12777 |
1 |
|
|
T1 |
27 |
|
T7 |
28 |
|
T4 |
1 |
app_invalid_sideload |
324598 |
1 |
|
|
T1 |
151 |
|
T2 |
161 |
|
T3 |
301 |