Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
10189182 | 
1 | 
 | 
 | 
T1 | 
26046 | 
 | 
T2 | 
26755 | 
 | 
T3 | 
3720 | 
| auto[1] | 
10189159 | 
1 | 
 | 
 | 
T1 | 
26046 | 
 | 
T2 | 
26755 | 
 | 
T3 | 
3720 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
4 | 
0 | 
4 | 
100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 
20146349 | 
1 | 
 | 
 | 
T1 | 
51872 | 
 | 
T2 | 
53246 | 
 | 
T3 | 
7440 | 
| triple_byte_access | 
77314 | 
1 | 
 | 
 | 
T1 | 
78 | 
 | 
T2 | 
88 | 
 | 
T7 | 
18 | 
| halfword_access | 
77910 | 
1 | 
 | 
 | 
T1 | 
64 | 
 | 
T2 | 
84 | 
 | 
T7 | 
30 | 
| byte_access | 
76768 | 
1 | 
 | 
 | 
T1 | 
78 | 
 | 
T2 | 
92 | 
 | 
T7 | 
22 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
8 | 
0 | 
8 | 
100.00 | 
 | 
Automatically Generated Cross Bins for state_mask_share_cross
Bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
word_access | 
10073186 | 
1 | 
 | 
 | 
T1 | 
25936 | 
 | 
T2 | 
26623 | 
 | 
T3 | 
3720 | 
| auto[0] | 
triple_byte_access | 
38657 | 
1 | 
 | 
 | 
T1 | 
39 | 
 | 
T2 | 
44 | 
 | 
T7 | 
9 | 
| auto[0] | 
halfword_access | 
38955 | 
1 | 
 | 
 | 
T1 | 
32 | 
 | 
T2 | 
42 | 
 | 
T7 | 
15 | 
| auto[0] | 
byte_access | 
38384 | 
1 | 
 | 
 | 
T1 | 
39 | 
 | 
T2 | 
46 | 
 | 
T7 | 
11 | 
| auto[1] | 
word_access | 
10073163 | 
1 | 
 | 
 | 
T1 | 
25936 | 
 | 
T2 | 
26623 | 
 | 
T3 | 
3720 | 
| auto[1] | 
triple_byte_access | 
38657 | 
1 | 
 | 
 | 
T1 | 
39 | 
 | 
T2 | 
44 | 
 | 
T7 | 
9 | 
| auto[1] | 
halfword_access | 
38955 | 
1 | 
 | 
 | 
T1 | 
32 | 
 | 
T2 | 
42 | 
 | 
T7 | 
15 | 
| auto[1] | 
byte_access | 
38384 | 
1 | 
 | 
 | 
T1 | 
39 | 
 | 
T2 | 
46 | 
 | 
T7 | 
11 |