Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100219629	1			T2	455959		T3	1000		T7	6625
all_values[1]	100219629	1			T2	455959		T3	1000		T7	6625
all_values[2]	100219629	1			T2	455959		T3	1000		T7	6625

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

531883

1

T2

23

T7

170

T8

41

auto[1]

300127004

1

T2

136785

T3

3000

T7

19705

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299135217

1

T2

135754

T3

2748

T7

19680

auto[1]

1523670

1

T2

10335

T3

252

T7

195

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	180013	1			T38	1266		T39	1		T40	61
all_values[0]	auto[0]	auto[1]	2026	1			T38	2		T39	2		T40	6
all_values[0]	auto[1]	auto[0]	99531726	1			T2	452514		T3	916		T7	6560
all_values[0]	auto[1]	auto[1]	505864	1			T2	3445		T3	84		T7	65
all_values[1]	auto[0]	auto[0]	155160	1			T2	4		T7	83		T8	40
all_values[1]	auto[0]	auto[1]	1512	1			T2	3		T7	2		T8	1
all_values[1]	auto[1]	auto[0]	99556579	1			T2	452510		T3	916		T7	6477
all_values[1]	auto[1]	auto[1]	506378	1			T2	3442		T3	84		T7	63
all_values[2]	auto[0]	auto[0]	191529	1			T2	9		T7	83		T39	1
all_values[2]	auto[0]	auto[1]	1643	1			T2	7		T7	2		T39	2
all_values[2]	auto[1]	auto[0]	99520210	1			T2	452505		T3	916		T7	6477
all_values[2]	auto[1]	auto[1]	506247	1			T2	3438		T3	84		T7	63