Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
315542 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T3 | 
2 | 
 | 
T7 | 
2 | 
| auto[1] | 
375910 | 
1 | 
 | 
 | 
T2 | 
4528 | 
 | 
T3 | 
114 | 
 | 
T7 | 
88 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
173501 | 
1 | 
 | 
 | 
T2 | 
1100 | 
 | 
T3 | 
14 | 
 | 
T7 | 
24 | 
| lower_val | 
171012 | 
1 | 
 | 
 | 
T2 | 
1167 | 
 | 
T3 | 
35 | 
 | 
T7 | 
20 | 
| zero_val | 
1760 | 
1 | 
 | 
 | 
T2 | 
11 | 
 | 
T3 | 
1 | 
 | 
T7 | 
1 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
251852 | 
1 | 
 | 
 | 
T2 | 
1120 | 
 | 
T3 | 
32 | 
 | 
T7 | 
22 | 
| lower_val | 
251052 | 
1 | 
 | 
 | 
T2 | 
1178 | 
 | 
T3 | 
10 | 
 | 
T7 | 
26 | 
| zero_val | 
188548 | 
1 | 
 | 
 | 
T2 | 
2232 | 
 | 
T3 | 
74 | 
 | 
T7 | 
42 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
18 | 
0 | 
18 | 
100.00 | 
 | 
Automatically Generated Cross Bins for entropy_timer_cross
Bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
higher_val | 
auto[0] | 
39962 | 
1 | 
 | 
 | 
T8 | 
7 | 
 | 
T37 | 
67 | 
 | 
T39 | 
70 | 
| higher_val | 
higher_val | 
auto[1] | 
23331 | 
1 | 
 | 
 | 
T2 | 
270 | 
 | 
T3 | 
1 | 
 | 
T7 | 
4 | 
| higher_val | 
lower_val | 
auto[0] | 
39693 | 
1 | 
 | 
 | 
T8 | 
17 | 
 | 
T37 | 
55 | 
 | 
T39 | 
77 | 
| higher_val | 
lower_val | 
auto[1] | 
23347 | 
1 | 
 | 
 | 
T2 | 
308 | 
 | 
T3 | 
2 | 
 | 
T7 | 
7 | 
| higher_val | 
zero_val | 
auto[0] | 
74 | 
1 | 
 | 
 | 
T7 | 
1 | 
 | 
T20 | 
1 | 
 | 
T68 | 
1 | 
| higher_val | 
zero_val | 
auto[1] | 
47094 | 
1 | 
 | 
 | 
T2 | 
522 | 
 | 
T3 | 
11 | 
 | 
T7 | 
12 | 
| lower_val | 
higher_val | 
auto[0] | 
38762 | 
1 | 
 | 
 | 
T8 | 
9 | 
 | 
T37 | 
53 | 
 | 
T39 | 
93 | 
| lower_val | 
higher_val | 
auto[1] | 
23161 | 
1 | 
 | 
 | 
T2 | 
310 | 
 | 
T3 | 
9 | 
 | 
T7 | 
6 | 
| lower_val | 
lower_val | 
auto[0] | 
38704 | 
1 | 
 | 
 | 
T8 | 
13 | 
 | 
T37 | 
67 | 
 | 
T39 | 
89 | 
| lower_val | 
lower_val | 
auto[1] | 
23355 | 
1 | 
 | 
 | 
T2 | 
289 | 
 | 
T3 | 
7 | 
 | 
T7 | 
7 | 
| lower_val | 
zero_val | 
auto[0] | 
85 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T6 | 
1 | 
 | 
T84 | 
1 | 
| lower_val | 
zero_val | 
auto[1] | 
46945 | 
1 | 
 | 
 | 
T2 | 
567 | 
 | 
T3 | 
19 | 
 | 
T7 | 
7 | 
| zero_val | 
higher_val | 
auto[0] | 
551 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T8 | 
1 | 
 | 
T37 | 
1 | 
| zero_val | 
higher_val | 
auto[1] | 
134 | 
1 | 
 | 
 | 
T2 | 
4 | 
 | 
T15 | 
1 | 
 | 
T202 | 
1 | 
| zero_val | 
lower_val | 
auto[0] | 
544 | 
1 | 
 | 
 | 
T38 | 
1 | 
 | 
T39 | 
1 | 
 | 
T42 | 
1 | 
| zero_val | 
lower_val | 
auto[1] | 
133 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T15 | 
2 | 
 | 
T202 | 
1 | 
| zero_val | 
zero_val | 
auto[0] | 
229 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T7 | 
1 | 
 | 
T6 | 
1 | 
| zero_val | 
zero_val | 
auto[1] | 
169 | 
1 | 
 | 
 | 
T2 | 
4 | 
 | 
T203 | 
5 | 
 | 
T204 | 
3 |