Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100219629	1			T2	455959		T3	1000		T7	6625
all_pins[1]	100219629	1			T2	455959		T3	1000		T7	6625
all_pins[2]	100219629	1			T2	455959		T3	1000		T7	6625

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299838720	1			T2	136443		T3	2916		T7	19803
values[0x1]	820167	1			T2	3445		T3	84		T7	72
transitions[0x0=>0x1]	818008	1			T2	3445		T3	84		T7	72
transitions[0x1=>0x0]	818035	1			T2	3445		T3	84		T7	72

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99713765	1			T2	452514		T3	916		T7	6560
all_pins[0]	values[0x1]	505864	1			T2	3445		T3	84		T7	65
all_pins[0]	transitions[0x0=>0x1]	505845	1			T2	3445		T3	84		T7	65
all_pins[0]	transitions[0x1=>0x0]	5851	1			T45	2		T46	27		T197	1
all_pins[1]	values[0x0]	100213759	1			T2	455959		T3	1000		T7	6625
all_pins[1]	values[0x1]	5870	1			T45	2		T46	27		T197	1
all_pins[1]	transitions[0x0=>0x1]	5613	1			T45	2		T46	27		T197	1
all_pins[1]	transitions[0x1=>0x0]	308176	1			T7	7		T15	10252		T23	146
all_pins[2]	values[0x0]	99911196	1			T2	455959		T3	1000		T7	6618
all_pins[2]	values[0x1]	308433	1			T7	7		T15	10252		T23	146
all_pins[2]	transitions[0x0=>0x1]	306550	1			T7	7		T15	10191		T23	145
all_pins[2]	transitions[0x1=>0x0]	504008	1			T2	3445		T3	84		T7	65