Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	666	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5623	1			T3	14		T7	3		T8	6
len_601_800	12825	1			T3	20		T7	14		T8	7
len_401_600	8465	1			T3	7		T7	9		T8	9
len_201_400	16516	1			T2	251		T3	5		T7	8
len_65_200	72929	1			T2	680		T3	8		T7	2
len_min_for_xof_require_squeeze	994	1			T2	10		T73	10		T74	10
len_keccak_block_sizes[72]	739	1			T2	5		T73	5		T74	5
len_keccak_block_sizes[104]	740	1			T2	5		T73	5		T74	5
len_keccak_block_sizes[136]	754	1			T2	5		T38	1		T73	5
len_keccak_block_sizes[144]	275	1			T2	5		T73	5		T74	5
len_keccak_block_sizes[168]	280	1			T2	5		T3	1		T42	1
len_datapath_width	14022	1			T2	5		T3	1		T37	246
len_2_63	212908	1			T2	1329		T3	3		T7	4
len_1	66	1			T15	1		T205	1		T135	2