Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10841004 |
1 |
|
|
T2 |
47900 |
|
T3 |
9205 |
|
T7 |
6656 |
auto[1] |
10840986 |
1 |
|
|
T2 |
47900 |
|
T3 |
9205 |
|
T7 |
6656 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21444584 |
1 |
|
|
T2 |
93928 |
|
T3 |
18328 |
|
T7 |
13244 |
triple_byte_access |
79060 |
1 |
|
|
T2 |
620 |
|
T3 |
16 |
|
T7 |
22 |
halfword_access |
79414 |
1 |
|
|
T2 |
632 |
|
T3 |
32 |
|
T7 |
22 |
byte_access |
78932 |
1 |
|
|
T2 |
620 |
|
T3 |
34 |
|
T7 |
24 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10722301 |
1 |
|
|
T2 |
46964 |
|
T3 |
9164 |
|
T7 |
6622 |
auto[0] |
triple_byte_access |
39530 |
1 |
|
|
T2 |
310 |
|
T3 |
8 |
|
T7 |
11 |
auto[0] |
halfword_access |
39707 |
1 |
|
|
T2 |
316 |
|
T3 |
16 |
|
T7 |
11 |
auto[0] |
byte_access |
39466 |
1 |
|
|
T2 |
310 |
|
T3 |
17 |
|
T7 |
12 |
auto[1] |
word_access |
10722283 |
1 |
|
|
T2 |
46964 |
|
T3 |
9164 |
|
T7 |
6622 |
auto[1] |
triple_byte_access |
39530 |
1 |
|
|
T2 |
310 |
|
T3 |
8 |
|
T7 |
11 |
auto[1] |
halfword_access |
39707 |
1 |
|
|
T2 |
316 |
|
T3 |
16 |
|
T7 |
11 |
auto[1] |
byte_access |
39466 |
1 |
|
|
T2 |
310 |
|
T3 |
17 |
|
T7 |
12 |