Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101090425	1			T2	288		T3	1		T17	13757
all_values[1]	101090425	1			T2	288		T3	1		T17	13757
all_values[2]	101090425	1			T2	288		T3	1		T17	13757

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

559547

1

T2

87

T3

1

T17

364

auto[1]

302711728

1

T2

777

T3

2

T17

40907

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301739436

1

T2

825

T3

3

T17

40863

auto[1]

1531839

1

T2

39

T17

408

T20

1095

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	221598	1			T37	3		T36	4		T41	3
all_values[0]	auto[0]	auto[1]	2048	1			T37	4		T36	2		T41	4
all_values[0]	auto[1]	auto[0]	100358214	1			T2	275		T3	1		T17	13621
all_values[0]	auto[1]	auto[1]	508565	1			T2	13		T17	136		T20	365
all_values[1]	auto[0]	auto[0]	186662	1			T2	77		T17	362		T37	1
all_values[1]	auto[0]	auto[1]	1586	1			T2	4		T17	2		T37	2
all_values[1]	auto[1]	auto[0]	100393150	1			T2	198		T3	1		T17	13259
all_values[1]	auto[1]	auto[1]	509027	1			T2	9		T17	134		T20	365
all_values[2]	auto[0]	auto[0]	146161	1			T2	5		T3	1		T20	10
all_values[2]	auto[0]	auto[1]	1492	1			T2	1		T20	5		T36	2
all_values[2]	auto[1]	auto[0]	100433651	1			T2	270		T17	13621		T20	110547
all_values[2]	auto[1]	auto[1]	509121	1			T2	12		T17	136		T20	360