Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350158 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T17 |
180 |
auto[1] |
344142 |
1 |
|
|
T2 |
16 |
|
T21 |
106 |
|
T41 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173727 |
1 |
|
|
T2 |
7 |
|
T17 |
47 |
|
T20 |
126 |
lower_val |
172965 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T17 |
40 |
zero_val |
1777 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
261744 |
1 |
|
|
T2 |
4 |
|
T17 |
98 |
|
T20 |
256 |
lower_val |
260086 |
1 |
|
|
T3 |
2 |
|
T17 |
82 |
|
T20 |
236 |
zero_val |
172470 |
1 |
|
|
T2 |
14 |
|
T21 |
48 |
|
T41 |
220 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43889 |
1 |
|
|
T17 |
25 |
|
T20 |
64 |
|
T37 |
611 |
higher_val |
higher_val |
auto[1] |
21712 |
1 |
|
|
T2 |
1 |
|
T21 |
3 |
|
T41 |
33 |
higher_val |
lower_val |
auto[0] |
43521 |
1 |
|
|
T17 |
22 |
|
T20 |
62 |
|
T37 |
570 |
higher_val |
lower_val |
auto[1] |
21462 |
1 |
|
|
T21 |
8 |
|
T41 |
41 |
|
T7 |
10 |
higher_val |
zero_val |
auto[0] |
86 |
1 |
|
|
T63 |
1 |
|
T18 |
1 |
|
T211 |
1 |
higher_val |
zero_val |
auto[1] |
43057 |
1 |
|
|
T2 |
6 |
|
T21 |
11 |
|
T41 |
60 |
lower_val |
higher_val |
auto[0] |
43217 |
1 |
|
|
T17 |
21 |
|
T20 |
63 |
|
T37 |
575 |
lower_val |
higher_val |
auto[1] |
21530 |
1 |
|
|
T2 |
2 |
|
T21 |
6 |
|
T41 |
27 |
lower_val |
lower_val |
auto[0] |
43408 |
1 |
|
|
T3 |
1 |
|
T17 |
19 |
|
T20 |
52 |
lower_val |
lower_val |
auto[1] |
21546 |
1 |
|
|
T21 |
4 |
|
T41 |
36 |
|
T7 |
5 |
lower_val |
zero_val |
auto[0] |
81 |
1 |
|
|
T2 |
1 |
|
T96 |
1 |
|
T43 |
1 |
lower_val |
zero_val |
auto[1] |
43183 |
1 |
|
|
T2 |
1 |
|
T21 |
9 |
|
T41 |
57 |
zero_val |
higher_val |
auto[0] |
555 |
1 |
|
|
T17 |
1 |
|
T37 |
2 |
|
T36 |
1 |
zero_val |
higher_val |
auto[1] |
138 |
1 |
|
|
T7 |
1 |
|
T43 |
2 |
|
T71 |
1 |
zero_val |
lower_val |
auto[0] |
531 |
1 |
|
|
T3 |
1 |
|
T20 |
1 |
|
T37 |
1 |
zero_val |
lower_val |
auto[1] |
132 |
1 |
|
|
T43 |
1 |
|
T212 |
1 |
|
T14 |
1 |
zero_val |
zero_val |
auto[0] |
240 |
1 |
|
|
T2 |
1 |
|
T21 |
1 |
|
T81 |
1 |
zero_val |
zero_val |
auto[1] |
181 |
1 |
|
|
T42 |
2 |
|
T43 |
1 |
|
T71 |
1 |