Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101090425	1			T2	288		T3	1		T17	13757
all_pins[1]	101090425	1			T2	288		T3	1		T17	13757
all_pins[2]	101090425	1			T2	288		T3	1		T17	13757

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	302500775	1			T2	851		T3	3		T17	41085
values[0x1]	770500	1			T2	13		T17	186		T20	365
transitions[0x0=>0x1]	768746	1			T2	13		T17	186		T20	365
transitions[0x1=>0x0]	768774	1			T2	13		T17	186		T20	365

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100581860	1			T2	275		T3	1		T17	13621
all_pins[0]	values[0x1]	508565	1			T2	13		T17	136		T20	365
all_pins[0]	transitions[0x0=>0x1]	508550	1			T2	13		T17	136		T20	365
all_pins[0]	transitions[0x1=>0x0]	6398	1			T17	50		T6	12		T39	6
all_pins[1]	values[0x0]	101084012	1			T2	288		T3	1		T17	13707
all_pins[1]	values[0x1]	6413	1			T17	50		T6	12		T39	6
all_pins[1]	transitions[0x0=>0x1]	6180	1			T17	50		T6	12		T39	6
all_pins[1]	transitions[0x1=>0x0]	255289	1			T22	586		T23	892		T14	6043
all_pins[2]	values[0x0]	100834903	1			T2	288		T3	1		T17	13757
all_pins[2]	values[0x1]	255522	1			T22	586		T23	892		T14	6065
all_pins[2]	transitions[0x0=>0x1]	254016	1			T22	586		T23	891		T14	6026
all_pins[2]	transitions[0x1=>0x0]	507087	1			T2	13		T17	136		T20	365