Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	649	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5571	1			T17	12		T6	1		T39	1
len_601_800	12680	1			T17	33		T6	12		T39	4
len_401_600	8287	1			T17	24		T6	7		T39	1
len_201_400	16501	1			T17	9		T37	251		T6	3
len_65_200	73905	1			T17	7		T37	680		T6	3
len_min_for_xof_require_squeeze	999	1			T37	10		T52	9		T42	10
len_keccak_block_sizes[72]	753	1			T37	5		T52	9		T7	1
len_keccak_block_sizes[104]	754	1			T37	5		T52	9		T42	5
len_keccak_block_sizes[136]	757	1			T37	5		T52	9		T42	5
len_keccak_block_sizes[144]	280	1			T37	5		T42	5		T68	5
len_keccak_block_sizes[168]	278	1			T37	5		T42	5		T68	5
len_datapath_width	14062	1			T2	3		T20	246		T37	5
len_2_63	213972	1			T2	6		T17	3		T37	1329
len_1	59	1			T70	1		T66	2		T213	1