Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99377299	1			T1	565757		T2	569237		T3	573884
all_values[1]	99377299	1			T1	565757		T2	569237		T3	573884
all_values[2]	99377299	1			T1	565757		T2	569237		T3	573884

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

514870

1

T1

24

T2

6

T3

20

auto[1]

297617027

1

T1

169724

T2

170770

T3

172163

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296607810

1

T1

168675

T2

169722

T3

171123

auto[1]

1524087

1

T1

10515

T2

10491

T3

10419

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	197956	1			T1	11		T2	1		T3	10
all_values[0]	auto[0]	auto[1]	2220	1			T1	10		T2	2		T3	10
all_values[0]	auto[1]	auto[0]	98671314	1			T1	562241		T2	565739		T3	570401
all_values[0]	auto[1]	auto[1]	505809	1			T1	3495		T2	3495		T3	3463
all_values[1]	auto[0]	auto[0]	134908	1			T7	309		T32	4		T34	191
all_values[1]	auto[0]	auto[1]	1510	1			T7	10		T32	2		T34	1
all_values[1]	auto[1]	auto[0]	98734362	1			T1	562252		T2	565740		T3	570411
all_values[1]	auto[1]	auto[1]	506519	1			T1	3505		T2	3497		T3	3473
all_values[2]	auto[0]	auto[0]	176711	1			T1	1		T2	1		T7	6859
all_values[2]	auto[0]	auto[1]	1565	1			T1	2		T2	2		T7	22
all_values[2]	auto[1]	auto[0]	98692559	1			T1	562251		T2	565739		T3	570411
all_values[2]	auto[1]	auto[1]	506464	1			T1	3503		T2	3495		T3	3473