Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
353338 |
1 |
|
|
T1 |
4674 |
|
T2 |
4674 |
|
T3 |
2 |
auto[1] |
336834 |
1 |
|
|
T3 |
4672 |
|
T7 |
310 |
|
T32 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173289 |
1 |
|
|
T1 |
1208 |
|
T2 |
1185 |
|
T3 |
1201 |
lower_val |
170232 |
1 |
|
|
T1 |
1224 |
|
T2 |
1132 |
|
T3 |
1148 |
zero_val |
1719 |
1 |
|
|
T1 |
3 |
|
T2 |
7 |
|
T3 |
7 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
260126 |
1 |
|
|
T1 |
2348 |
|
T2 |
2384 |
|
T3 |
1200 |
lower_val |
261416 |
1 |
|
|
T1 |
2326 |
|
T2 |
2290 |
|
T3 |
1134 |
zero_val |
168630 |
1 |
|
|
T3 |
2340 |
|
T7 |
144 |
|
T32 |
8 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44139 |
1 |
|
|
T1 |
602 |
|
T2 |
631 |
|
T3 |
1 |
higher_val |
higher_val |
auto[1] |
20906 |
1 |
|
|
T3 |
331 |
|
T7 |
17 |
|
T32 |
3 |
higher_val |
lower_val |
auto[0] |
44494 |
1 |
|
|
T1 |
606 |
|
T2 |
554 |
|
T7 |
64 |
higher_val |
lower_val |
auto[1] |
21404 |
1 |
|
|
T3 |
298 |
|
T7 |
13 |
|
T35 |
53 |
higher_val |
zero_val |
auto[0] |
83 |
1 |
|
|
T7 |
1 |
|
T186 |
1 |
|
T93 |
1 |
higher_val |
zero_val |
auto[1] |
42263 |
1 |
|
|
T3 |
571 |
|
T7 |
22 |
|
T35 |
102 |
lower_val |
higher_val |
auto[0] |
43315 |
1 |
|
|
T1 |
600 |
|
T2 |
582 |
|
T7 |
67 |
lower_val |
higher_val |
auto[1] |
20860 |
1 |
|
|
T3 |
282 |
|
T7 |
31 |
|
T32 |
1 |
lower_val |
lower_val |
auto[0] |
43521 |
1 |
|
|
T1 |
624 |
|
T2 |
550 |
|
T7 |
55 |
lower_val |
lower_val |
auto[1] |
20809 |
1 |
|
|
T3 |
285 |
|
T7 |
16 |
|
T32 |
2 |
lower_val |
zero_val |
auto[0] |
89 |
1 |
|
|
T7 |
3 |
|
T39 |
1 |
|
T57 |
1 |
lower_val |
zero_val |
auto[1] |
41638 |
1 |
|
|
T3 |
581 |
|
T7 |
49 |
|
T32 |
5 |
zero_val |
higher_val |
auto[0] |
525 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
114 |
1 |
|
|
T7 |
3 |
|
T76 |
2 |
|
T90 |
1 |
zero_val |
lower_val |
auto[0] |
528 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T7 |
2 |
zero_val |
lower_val |
auto[1] |
115 |
1 |
|
|
T3 |
2 |
|
T76 |
2 |
|
T186 |
1 |
zero_val |
zero_val |
auto[0] |
249 |
1 |
|
|
T7 |
1 |
|
T34 |
1 |
|
T38 |
1 |
zero_val |
zero_val |
auto[1] |
188 |
1 |
|
|
T3 |
4 |
|
T7 |
2 |
|
T76 |
2 |