Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99377299	1			T1	565757		T2	569237		T3	573884
all_pins[1]	99377299	1			T1	565757		T2	569237		T3	573884
all_pins[2]	99377299	1			T1	565757		T2	569237		T3	573884

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297344269	1			T1	169377		T2	170421		T3	171818
values[0x1]	787628	1			T1	3495		T2	3495		T3	3463
transitions[0x0=>0x1]	785811	1			T1	3495		T2	3495		T3	3463
transitions[0x1=>0x0]	785838	1			T1	3495		T2	3495		T3	3463

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98871490	1			T1	562262		T2	565742		T3	570421
all_pins[0]	values[0x1]	505809	1			T1	3495		T2	3495		T3	3463
all_pins[0]	transitions[0x0=>0x1]	505800	1			T1	3495		T2	3495		T3	3463
all_pins[0]	transitions[0x1=>0x0]	6614	1			T9	41		T33	30		T10	34
all_pins[1]	values[0x0]	99370676	1			T1	565757		T2	569237		T3	573884
all_pins[1]	values[0x1]	6623	1			T9	41		T33	30		T10	34
all_pins[1]	transitions[0x0=>0x1]	6480	1			T9	41		T33	30		T10	34
all_pins[1]	transitions[0x1=>0x0]	275053	1			T7	6380		T9	120		T16	22144
all_pins[2]	values[0x0]	99102103	1			T1	565757		T2	569237		T3	573884
all_pins[2]	values[0x1]	275196	1			T7	6380		T9	120		T16	22144
all_pins[2]	transitions[0x0=>0x1]	273531	1			T7	6339		T9	120		T16	21999
all_pins[2]	transitions[0x1=>0x0]	504171	1			T1	3495		T2	3495		T3	3463