Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99757984	1			T1	1679		T2	1507		T3	3828
all_values[1]	99757984	1			T1	1679		T2	1507		T3	3828
all_values[2]	99757984	1			T1	1679		T2	1507		T3	3828

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

573263

1

T1

23

T2

225

T3

53

auto[1]

298700689

1

T1

5014

T2

4296

T3

11431

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297749382

1

T1

4284

T2

4113

T3

11175

auto[1]

1524570

1

T1

753

T2

408

T3

309

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	171533	1			T3	48		T20	6		T34	58
all_values[0]	auto[0]	auto[1]	1896	1			T3	2		T20	2		T34	2
all_values[0]	auto[1]	auto[0]	99078261	1			T1	1428		T2	1371		T3	3677
all_values[0]	auto[1]	auto[1]	506294	1			T1	251		T2	136		T3	101
all_values[1]	auto[0]	auto[0]	189888	1			T2	74		T3	2		T7	268
all_values[1]	auto[0]	auto[1]	1535	1			T2	5		T7	2		T15	7
all_values[1]	auto[1]	auto[0]	99059906	1			T1	1428		T2	1297		T3	3723
all_values[1]	auto[1]	auto[1]	506655	1			T1	251		T2	131		T3	103
all_values[2]	auto[0]	auto[0]	206846	1			T1	18		T2	133		T3	1
all_values[2]	auto[0]	auto[1]	1565	1			T1	5		T2	13		T20	3
all_values[2]	auto[1]	auto[0]	99042948	1			T1	1410		T2	1238		T3	3724
all_values[2]	auto[1]	auto[1]	506625	1			T1	246		T2	123		T3	103