Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
331382 | 
1 | 
 | 
 | 
T1 | 
320 | 
 | 
T2 | 
184 | 
 | 
T3 | 
172 | 
| auto[1] | 
359908 | 
1 | 
 | 
 | 
T8 | 
98 | 
 | 
T33 | 
4672 | 
 | 
T36 | 
4672 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
173632 | 
1 | 
 | 
 | 
T1 | 
72 | 
 | 
T2 | 
53 | 
 | 
T3 | 
51 | 
| lower_val | 
171994 | 
1 | 
 | 
 | 
T1 | 
104 | 
 | 
T2 | 
44 | 
 | 
T3 | 
40 | 
| zero_val | 
1836 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
2 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
255232 | 
1 | 
 | 
 | 
T1 | 
162 | 
 | 
T2 | 
100 | 
 | 
T3 | 
80 | 
| lower_val | 
256472 | 
1 | 
 | 
 | 
T1 | 
158 | 
 | 
T2 | 
84 | 
 | 
T3 | 
92 | 
| zero_val | 
179586 | 
1 | 
 | 
 | 
T8 | 
58 | 
 | 
T33 | 
2378 | 
 | 
T36 | 
2344 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
18 | 
0 | 
18 | 
100.00 | 
 | 
Automatically Generated Cross Bins for entropy_timer_cross
Bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
higher_val | 
auto[0] | 
41596 | 
1 | 
 | 
 | 
T1 | 
36 | 
 | 
T2 | 
31 | 
 | 
T3 | 
26 | 
| higher_val | 
higher_val | 
auto[1] | 
22825 | 
1 | 
 | 
 | 
T8 | 
6 | 
 | 
T33 | 
258 | 
 | 
T36 | 
317 | 
| higher_val | 
lower_val | 
auto[0] | 
41542 | 
1 | 
 | 
 | 
T1 | 
36 | 
 | 
T2 | 
22 | 
 | 
T3 | 
25 | 
| higher_val | 
lower_val | 
auto[1] | 
22737 | 
1 | 
 | 
 | 
T8 | 
1 | 
 | 
T33 | 
286 | 
 | 
T36 | 
281 | 
| higher_val | 
zero_val | 
auto[0] | 
85 | 
1 | 
 | 
 | 
T128 | 
1 | 
 | 
T201 | 
1 | 
 | 
T202 | 
1 | 
| higher_val | 
zero_val | 
auto[1] | 
44847 | 
1 | 
 | 
 | 
T8 | 
14 | 
 | 
T33 | 
581 | 
 | 
T36 | 
605 | 
| lower_val | 
higher_val | 
auto[0] | 
40904 | 
1 | 
 | 
 | 
T1 | 
50 | 
 | 
T2 | 
16 | 
 | 
T3 | 
21 | 
| lower_val | 
higher_val | 
auto[1] | 
22203 | 
1 | 
 | 
 | 
T8 | 
6 | 
 | 
T33 | 
269 | 
 | 
T36 | 
271 | 
| lower_val | 
lower_val | 
auto[0] | 
41307 | 
1 | 
 | 
 | 
T1 | 
54 | 
 | 
T2 | 
28 | 
 | 
T3 | 
19 | 
| lower_val | 
lower_val | 
auto[1] | 
22649 | 
1 | 
 | 
 | 
T8 | 
7 | 
 | 
T33 | 
287 | 
 | 
T36 | 
261 | 
| lower_val | 
zero_val | 
auto[0] | 
90 | 
1 | 
 | 
 | 
T36 | 
1 | 
 | 
T15 | 
1 | 
 | 
T89 | 
1 | 
| lower_val | 
zero_val | 
auto[1] | 
44841 | 
1 | 
 | 
 | 
T8 | 
17 | 
 | 
T33 | 
618 | 
 | 
T36 | 
557 | 
| zero_val | 
higher_val | 
auto[0] | 
574 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T7 | 
1 | 
| zero_val | 
higher_val | 
auto[1] | 
137 | 
1 | 
 | 
 | 
T33 | 
2 | 
 | 
T36 | 
2 | 
 | 
T15 | 
1 | 
| zero_val | 
lower_val | 
auto[0] | 
484 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T20 | 
1 | 
 | 
T15 | 
3 | 
| zero_val | 
lower_val | 
auto[1] | 
150 | 
1 | 
 | 
 | 
T33 | 
3 | 
 | 
T36 | 
2 | 
 | 
T15 | 
1 | 
| zero_val | 
zero_val | 
auto[0] | 
268 | 
1 | 
 | 
 | 
T36 | 
1 | 
 | 
T15 | 
1 | 
 | 
T65 | 
1 | 
| zero_val | 
zero_val | 
auto[1] | 
223 | 
1 | 
 | 
 | 
T33 | 
5 | 
 | 
T36 | 
2 | 
 | 
T15 | 
2 |