Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10313	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8949	1			T2	22		T33	30		T36	30
len_5001_7500	14280	1			T2	39		T33	30		T36	30
len_2501_5000	9191	1			T2	13		T33	30		T36	30
len_1025_2500	5374	1			T2	5		T33	16		T36	16
len_769_1024	6248	1			T3	4		T7	18		T8	6
len_513_768	6612	1			T2	2		T3	6		T7	24
len_257_512	21103	1			T3	8		T7	30		T8	6
len_0_256	256551	1			T1	160		T2	11		T3	48
len_keccak_block_sizes[72]	722	1			T33	3		T36	3		T37	3
len_keccak_block_sizes[104]	618	1			T33	3		T36	3		T37	3
len_keccak_block_sizes[136]	520	1			T33	3		T36	3		T37	3
len_keccak_block_sizes[144]	430	1			T33	3		T36	3		T37	3
len_keccak_block_sizes[168]	318	1			T33	3		T36	3		T37	3
len_1	750	1			T1	2		T3	1		T33	3
len_0	1199	1			T1	2		T2	2		T3	2