Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99757984	1			T1	1679		T2	1507		T3	3828
all_pins[1]	99757984	1			T1	1679		T2	1507		T3	3828
all_pins[2]	99757984	1			T1	1679		T2	1507		T3	3828

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298424898	1			T1	4786		T2	4385		T3	11383
values[0x1]	849054	1			T1	251		T2	136		T3	101
transitions[0x0=>0x1]	846673	1			T1	251		T2	136		T3	101
transitions[0x1=>0x0]	846696	1			T1	251		T2	136		T3	101

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99251690	1			T1	1428		T2	1371		T3	3727
all_pins[0]	values[0x1]	506294	1			T1	251		T2	136		T3	101
all_pins[0]	transitions[0x0=>0x1]	506286	1			T1	251		T2	136		T3	101
all_pins[0]	transitions[0x1=>0x0]	5123	1			T8	14		T20	56		T35	15
all_pins[1]	values[0x0]	99752853	1			T1	1679		T2	1507		T3	3828
all_pins[1]	values[0x1]	5131	1			T8	14		T20	56		T35	15
all_pins[1]	transitions[0x0=>0x1]	4808	1			T8	14		T20	56		T35	15
all_pins[1]	transitions[0x1=>0x0]	337306	1			T20	222		T15	4870		T21	326
all_pins[2]	values[0x0]	99420355	1			T1	1679		T2	1507		T3	3828
all_pins[2]	values[0x1]	337629	1			T20	222		T15	4882		T21	326
all_pins[2]	transitions[0x0=>0x1]	335579	1			T20	222		T15	4847		T21	326
all_pins[2]	transitions[0x1=>0x0]	504267	1			T1	251		T2	136		T3	101