Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	639	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5533	1			T2	24		T3	5		T7	13
len_601_800	12340	1			T2	28		T3	10		T7	33
len_401_600	8204	1			T2	21		T3	6		T7	21
len_201_400	16398	1			T2	7		T3	2		T7	11
len_65_200	73637	1			T1	82		T2	5		T3	21
len_min_for_xof_require_squeeze	1004	1			T33	9		T36	9		T37	9
len_keccak_block_sizes[72]	750	1			T1	1		T33	9		T36	9
len_keccak_block_sizes[104]	746	1			T1	2		T7	1		T33	9
len_keccak_block_sizes[136]	769	1			T1	1		T33	9		T34	1
len_keccak_block_sizes[144]	299	1			T128	1		T202	5		T162	1
len_keccak_block_sizes[168]	276	1			T39	1		T202	5		T203	5
len_datapath_width	13830	1			T1	6		T3	1		T33	9
len_2_63	213371	1			T1	70		T2	5		T3	41
len_1	50	1			T1	2		T65	1		T204	1