Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10676363 |
1 |
|
|
T1 |
5658 |
|
T2 |
15856 |
|
T3 |
6367 |
auto[1] |
10676275 |
1 |
|
|
T1 |
5658 |
|
T2 |
15856 |
|
T3 |
6367 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21115088 |
1 |
|
|
T1 |
11108 |
|
T2 |
31578 |
|
T3 |
12646 |
triple_byte_access |
78990 |
1 |
|
|
T1 |
84 |
|
T2 |
36 |
|
T3 |
22 |
halfword_access |
79532 |
1 |
|
|
T1 |
62 |
|
T2 |
46 |
|
T3 |
40 |
byte_access |
79028 |
1 |
|
|
T1 |
62 |
|
T2 |
52 |
|
T3 |
26 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10557588 |
1 |
|
|
T1 |
5554 |
|
T2 |
15789 |
|
T3 |
6323 |
auto[0] |
triple_byte_access |
39495 |
1 |
|
|
T1 |
42 |
|
T2 |
18 |
|
T3 |
11 |
auto[0] |
halfword_access |
39766 |
1 |
|
|
T1 |
31 |
|
T2 |
23 |
|
T3 |
20 |
auto[0] |
byte_access |
39514 |
1 |
|
|
T1 |
31 |
|
T2 |
26 |
|
T3 |
13 |
auto[1] |
word_access |
10557500 |
1 |
|
|
T1 |
5554 |
|
T2 |
15789 |
|
T3 |
6323 |
auto[1] |
triple_byte_access |
39495 |
1 |
|
|
T1 |
42 |
|
T2 |
18 |
|
T3 |
11 |
auto[1] |
halfword_access |
39766 |
1 |
|
|
T1 |
31 |
|
T2 |
23 |
|
T3 |
20 |
auto[1] |
byte_access |
39514 |
1 |
|
|
T1 |
31 |
|
T2 |
26 |
|
T3 |
13 |