Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98602638	1			T1	16584		T2	478		T3	1974
all_values[1]	98602638	1			T1	16584		T2	478		T3	1974
all_values[2]	98602638	1			T1	16584		T2	478		T3	1974

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

523620

1

T1

396

T2

63

T7

274

auto[1]

295284294

1

T1

49356

T2

1371

T3

5922

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294300258

1

T1

49245

T2

1290

T3

5874

auto[1]

1507656

1

T1

507

T2

144

T3

48

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	162495	1			T2	40		T37	1		T11	17
all_values[0]	auto[0]	auto[1]	2082	1			T2	6		T37	2		T38	4
all_values[0]	auto[1]	auto[0]	97937591	1			T1	16415		T2	390		T3	1958
all_values[0]	auto[1]	auto[1]	500470	1			T1	169		T2	42		T3	16
all_values[1]	auto[0]	auto[0]	181420	1			T1	393		T2	15		T7	273
all_values[1]	auto[0]	auto[1]	1560	1			T1	3		T2	2		T7	1
all_values[1]	auto[1]	auto[0]	97918666	1			T1	16022		T2	415		T3	1958
all_values[1]	auto[1]	auto[1]	500992	1			T1	166		T2	46		T3	16
all_values[2]	auto[0]	auto[0]	174710	1			T40	3		T12	4		T184	2
all_values[2]	auto[0]	auto[1]	1353	1			T40	4		T184	1		T21	2
all_values[2]	auto[1]	auto[0]	97925376	1			T1	16415		T2	430		T3	1958
all_values[2]	auto[1]	auto[1]	501199	1			T1	169		T2	48		T3	16