Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
352278 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
330910 |
1 |
|
|
T1 |
336 |
|
T2 |
56 |
|
T3 |
26 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171390 |
1 |
|
|
T1 |
102 |
|
T2 |
17 |
|
T3 |
4 |
lower_val |
169116 |
1 |
|
|
T1 |
78 |
|
T2 |
12 |
|
T3 |
10 |
zero_val |
1762 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
259480 |
1 |
|
|
T1 |
72 |
|
T2 |
10 |
|
T3 |
8 |
lower_val |
258064 |
1 |
|
|
T1 |
68 |
|
T2 |
18 |
|
T3 |
2 |
zero_val |
165644 |
1 |
|
|
T1 |
198 |
|
T2 |
30 |
|
T3 |
18 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44070 |
1 |
|
|
T38 |
597 |
|
T197 |
1 |
|
T72 |
90 |
higher_val |
higher_val |
auto[1] |
20751 |
1 |
|
|
T1 |
22 |
|
T2 |
4 |
|
T3 |
1 |
higher_val |
lower_val |
auto[0] |
43999 |
1 |
|
|
T38 |
577 |
|
T39 |
1 |
|
T72 |
76 |
higher_val |
lower_val |
auto[1] |
20946 |
1 |
|
|
T1 |
21 |
|
T2 |
6 |
|
T7 |
4 |
higher_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T2 |
1 |
|
T184 |
1 |
|
T198 |
1 |
higher_val |
zero_val |
auto[1] |
41544 |
1 |
|
|
T1 |
59 |
|
T2 |
6 |
|
T3 |
3 |
lower_val |
higher_val |
auto[0] |
43778 |
1 |
|
|
T37 |
1 |
|
T38 |
594 |
|
T72 |
98 |
lower_val |
higher_val |
auto[1] |
20784 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
4 |
lower_val |
lower_val |
auto[0] |
43057 |
1 |
|
|
T38 |
537 |
|
T41 |
1 |
|
T12 |
1 |
lower_val |
lower_val |
auto[1] |
20546 |
1 |
|
|
T1 |
19 |
|
T2 |
4 |
|
T3 |
1 |
lower_val |
zero_val |
auto[0] |
68 |
1 |
|
|
T40 |
1 |
|
T111 |
1 |
|
T149 |
1 |
lower_val |
zero_val |
auto[1] |
40883 |
1 |
|
|
T1 |
46 |
|
T2 |
6 |
|
T3 |
5 |
zero_val |
higher_val |
auto[0] |
564 |
1 |
|
|
T7 |
1 |
|
T37 |
1 |
|
T36 |
1 |
zero_val |
higher_val |
auto[1] |
150 |
1 |
|
|
T37 |
1 |
|
T14 |
1 |
|
T55 |
1 |
zero_val |
lower_val |
auto[0] |
525 |
1 |
|
|
T11 |
1 |
|
T38 |
7 |
|
T39 |
1 |
zero_val |
lower_val |
auto[1] |
115 |
1 |
|
|
T7 |
1 |
|
T120 |
1 |
|
T199 |
1 |
zero_val |
zero_val |
auto[0] |
228 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
zero_val |
auto[1] |
180 |
1 |
|
|
T7 |
1 |
|
T37 |
1 |
|
T120 |
1 |