Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98602638	1			T1	16584		T2	478		T3	1974
all_pins[1]	98602638	1			T1	16584		T2	478		T3	1974
all_pins[2]	98602638	1			T1	16584		T2	478		T3	1974

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	294976836	1			T1	49553		T2	1369		T3	5905
values[0x1]	831078	1			T1	199		T2	65		T3	17
transitions[0x0=>0x1]	828798	1			T1	199		T2	65		T3	17
transitions[0x1=>0x0]	828823	1			T1	199		T2	65		T3	17

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98102168	1			T1	16415		T2	436		T3	1958
all_pins[0]	values[0x1]	500470	1			T1	169		T2	42		T3	16
all_pins[0]	transitions[0x0=>0x1]	500454	1			T1	169		T2	42		T3	16
all_pins[0]	transitions[0x1=>0x0]	5698	1			T1	30		T2	23		T3	1
all_pins[1]	values[0x0]	98596924	1			T1	16554		T2	455		T3	1973
all_pins[1]	values[0x1]	5714	1			T1	30		T2	23		T3	1
all_pins[1]	transitions[0x0=>0x1]	5419	1			T1	30		T2	23		T3	1
all_pins[1]	transitions[0x1=>0x0]	324599	1			T23	531		T14	327		T24	510
all_pins[2]	values[0x0]	98277744	1			T1	16584		T2	478		T3	1974
all_pins[2]	values[0x1]	324894	1			T23	531		T14	330		T24	510
all_pins[2]	transitions[0x0=>0x1]	322925	1			T23	531		T14	328		T24	510
all_pins[2]	transitions[0x1=>0x0]	498526	1			T1	169		T2	42		T3	16