Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	633	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5507	1			T1	17		T2	3		T3	3
len_601_800	12043	1			T1	42		T2	11		T3	4
len_401_600	7920	1			T1	29		T2	7		T3	1
len_201_400	16382	1			T1	15		T2	4		T36	17
len_65_200	72819	1			T1	6		T2	1		T3	1
len_min_for_xof_require_squeeze	991	1			T1	1		T38	9		T121	10
len_keccak_block_sizes[72]	748	1			T38	9		T71	1		T121	5
len_keccak_block_sizes[104]	747	1			T38	9		T121	5		T122	1
len_keccak_block_sizes[136]	744	1			T38	9		T121	5		T122	1
len_keccak_block_sizes[144]	277	1			T121	5		T124	1		T200	5
len_keccak_block_sizes[168]	283	1			T21	1		T121	5		T201	2
len_datapath_width	13706	1			T1	1		T7	1		T36	1
len_2_63	210759	1			T1	58		T2	2		T3	5
len_1	47	1			T71	1		T201	1		T202	1