Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
10502708 | 
1 | 
 | 
 | 
T1 | 
20332 | 
 | 
T2 | 
4641 | 
 | 
T3 | 
1824 | 
| auto[1] | 
10502648 | 
1 | 
 | 
 | 
T1 | 
20332 | 
 | 
T2 | 
4641 | 
 | 
T3 | 
1824 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
4 | 
0 | 
4 | 
100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 
20770942 | 
1 | 
 | 
 | 
T1 | 
40506 | 
 | 
T2 | 
9234 | 
 | 
T3 | 
3632 | 
| triple_byte_access | 
78018 | 
1 | 
 | 
 | 
T1 | 
44 | 
 | 
T2 | 
18 | 
 | 
T3 | 
10 | 
| halfword_access | 
78640 | 
1 | 
 | 
 | 
T1 | 
74 | 
 | 
T2 | 
12 | 
 | 
T3 | 
6 | 
| byte_access | 
77756 | 
1 | 
 | 
 | 
T1 | 
40 | 
 | 
T2 | 
18 | 
 | 
T7 | 
24 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
8 | 
0 | 
8 | 
100.00 | 
 | 
Automatically Generated Cross Bins for state_mask_share_cross
Bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
word_access | 
10385501 | 
1 | 
 | 
 | 
T1 | 
20253 | 
 | 
T2 | 
4617 | 
 | 
T3 | 
1816 | 
| auto[0] | 
triple_byte_access | 
39009 | 
1 | 
 | 
 | 
T1 | 
22 | 
 | 
T2 | 
9 | 
 | 
T3 | 
5 | 
| auto[0] | 
halfword_access | 
39320 | 
1 | 
 | 
 | 
T1 | 
37 | 
 | 
T2 | 
6 | 
 | 
T3 | 
3 | 
| auto[0] | 
byte_access | 
38878 | 
1 | 
 | 
 | 
T1 | 
20 | 
 | 
T2 | 
9 | 
 | 
T7 | 
12 | 
| auto[1] | 
word_access | 
10385441 | 
1 | 
 | 
 | 
T1 | 
20253 | 
 | 
T2 | 
4617 | 
 | 
T3 | 
1816 | 
| auto[1] | 
triple_byte_access | 
39009 | 
1 | 
 | 
 | 
T1 | 
22 | 
 | 
T2 | 
9 | 
 | 
T3 | 
5 | 
| auto[1] | 
halfword_access | 
39320 | 
1 | 
 | 
 | 
T1 | 
37 | 
 | 
T2 | 
6 | 
 | 
T3 | 
3 | 
| auto[1] | 
byte_access | 
38878 | 
1 | 
 | 
 | 
T1 | 
20 | 
 | 
T2 | 
9 | 
 | 
T7 | 
12 |