Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100250525	1			T1	19075		T3	210406		T17	459732
all_values[1]	100250525	1			T1	19075		T3	210406		T17	459732
all_values[2]	100250525	1			T1	19075		T3	210406		T17	459732

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

553524

1

T1

246

T3

10

T17

11

auto[1]

300198051

1

T1

56979

T3

631208

T17

137918

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299226918

1

T1

56682

T3

629532

T17

136902

auto[1]

1524657

1

T1

543

T3

1686

T17

10170

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	180931	1			T35	9		T36	4		T42	4
all_values[0]	auto[0]	auto[1]	2077	1			T35	4		T36	2		T42	2
all_values[0]	auto[1]	auto[0]	99561375	1			T1	18894		T3	209844		T17	456342
all_values[0]	auto[1]	auto[1]	506142	1			T1	181		T3	562		T17	3390
all_values[1]	auto[0]	auto[0]	174626	1			T1	245		T3	2		T17	8
all_values[1]	auto[0]	auto[1]	1465	1			T1	1		T3	1		T17	3
all_values[1]	auto[1]	auto[0]	99567680	1			T1	18649		T3	209842		T17	456334
all_values[1]	auto[1]	auto[1]	506754	1			T1	180		T3	561		T17	3387
all_values[2]	auto[0]	auto[0]	192841	1			T3	4		T35	9		T36	79
all_values[2]	auto[0]	auto[1]	1584	1			T3	3		T35	4		T36	4
all_values[2]	auto[1]	auto[0]	99549465	1			T1	18894		T3	209840		T17	456342
all_values[2]	auto[1]	auto[1]	506635	1			T1	181		T3	559		T17	3390