Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100250525	1			T1	19075		T3	210406		T17	459732
all_pins[1]	100250525	1			T1	19075		T3	210406		T17	459732
all_pins[2]	100250525	1			T1	19075		T3	210406		T17	459732

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299967638	1			T1	57044		T3	630656		T17	137580
values[0x1]	783937	1			T1	181		T3	562		T17	3390
transitions[0x0=>0x1]	782001	1			T1	181		T3	562		T17	3390
transitions[0x1=>0x0]	782023	1			T1	181		T3	562		T17	3390

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99744383	1			T1	18894		T3	209844		T17	456342
all_pins[0]	values[0x1]	506142	1			T1	181		T3	562		T17	3390
all_pins[0]	transitions[0x0=>0x1]	506135	1			T1	181		T3	562		T17	3390
all_pins[0]	transitions[0x1=>0x0]	6240	1			T35	2		T7	55		T18	18
all_pins[1]	values[0x0]	100244278	1			T1	19075		T3	210406		T17	459732
all_pins[1]	values[0x1]	6247	1			T35	2		T7	55		T18	18
all_pins[1]	transitions[0x0=>0x1]	5966	1			T35	2		T7	55		T18	18
all_pins[1]	transitions[0x1=>0x0]	271267	1			T7	813		T57	4		T14	4931
all_pins[2]	values[0x0]	99978977	1			T1	19075		T3	210406		T17	459732
all_pins[2]	values[0x1]	271548	1			T7	813		T57	4		T14	4942
all_pins[2]	transitions[0x0=>0x1]	269900	1			T7	813		T57	4		T14	4908
all_pins[2]	transitions[0x1=>0x0]	504516	1			T1	181		T3	562		T17	3390