Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10586610 |
1 |
|
|
T1 |
23203 |
|
T3 |
2992 |
|
T17 |
47900 |
auto[1] |
10586568 |
1 |
|
|
T1 |
23203 |
|
T3 |
2992 |
|
T17 |
47900 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20936432 |
1 |
|
|
T1 |
46228 |
|
T3 |
5984 |
|
T17 |
93928 |
triple_byte_access |
78828 |
1 |
|
|
T1 |
52 |
|
T17 |
620 |
|
T6 |
24 |
halfword_access |
79152 |
1 |
|
|
T1 |
54 |
|
T17 |
632 |
|
T6 |
18 |
byte_access |
78766 |
1 |
|
|
T1 |
72 |
|
T17 |
620 |
|
T6 |
32 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10468237 |
1 |
|
|
T1 |
23114 |
|
T3 |
2992 |
|
T17 |
46964 |
auto[0] |
triple_byte_access |
39414 |
1 |
|
|
T1 |
26 |
|
T17 |
310 |
|
T6 |
12 |
auto[0] |
halfword_access |
39576 |
1 |
|
|
T1 |
27 |
|
T17 |
316 |
|
T6 |
9 |
auto[0] |
byte_access |
39383 |
1 |
|
|
T1 |
36 |
|
T17 |
310 |
|
T6 |
16 |
auto[1] |
word_access |
10468195 |
1 |
|
|
T1 |
23114 |
|
T3 |
2992 |
|
T17 |
46964 |
auto[1] |
triple_byte_access |
39414 |
1 |
|
|
T1 |
26 |
|
T17 |
310 |
|
T6 |
12 |
auto[1] |
halfword_access |
39576 |
1 |
|
|
T1 |
27 |
|
T17 |
316 |
|
T6 |
9 |
auto[1] |
byte_access |
39383 |
1 |
|
|
T1 |
36 |
|
T17 |
310 |
|
T6 |
16 |