Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98897404	1			T1	461652		T2	209558		T3	370
all_values[1]	98897404	1			T1	461652		T2	209558		T3	370
all_values[2]	98897404	1			T1	461652		T2	209558		T3	370

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

587637

1

T2

14

T32

54

T7

680

auto[1]

296104575

1

T1

138495

T2

628660

T3

1110

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295185276

1

T1

137486

T2

626982

T3

1107

auto[1]

1506936

1

T1

10092

T2

1692

T3

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	192208	1			T2	1		T33	1		T38	3
all_values[0]	auto[0]	auto[1]	1900	1			T2	2		T33	2		T38	4
all_values[0]	auto[1]	auto[0]	98202884	1			T1	458288		T2	208993		T3	369
all_values[0]	auto[1]	auto[1]	500412	1			T1	3364		T2	562		T3	1
all_values[1]	auto[0]	auto[0]	188553	1			T32	37		T33	4		T35	4930
all_values[1]	auto[0]	auto[1]	1539	1			T32	6		T33	3		T35	3
all_values[1]	auto[1]	auto[0]	98206539	1			T1	458288		T2	208994		T3	369
all_values[1]	auto[1]	auto[1]	500773	1			T1	3364		T2	564		T3	1
all_values[2]	auto[0]	auto[0]	201855	1			T2	6		T32	10		T7	676
all_values[2]	auto[0]	auto[1]	1582	1			T2	5		T32	1		T7	4
all_values[2]	auto[1]	auto[0]	98193237	1			T1	458288		T2	208988		T3	369
all_values[2]	auto[1]	auto[1]	500730	1			T1	3364		T2	559		T3	1