Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
347250 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T2 | 
2 | 
 | 
T3 | 
2 | 
| auto[1] | 
336214 | 
1 | 
 | 
 | 
T1 | 
4528 | 
 | 
T2 | 
746 | 
 | 
T3 | 
6 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
170726 | 
1 | 
 | 
 | 
T1 | 
1142 | 
 | 
T2 | 
183 | 
 | 
T3 | 
1 | 
| lower_val | 
168660 | 
1 | 
 | 
 | 
T1 | 
1048 | 
 | 
T2 | 
188 | 
 | 
T3 | 
4 | 
| zero_val | 
1687 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
5 | 
 | 
T3 | 
1 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
257352 | 
1 | 
 | 
 | 
T1 | 
1110 | 
 | 
T2 | 
200 | 
 | 
T3 | 
4 | 
| lower_val | 
257606 | 
1 | 
 | 
 | 
T1 | 
1092 | 
 | 
T2 | 
178 | 
 | 
T32 | 
48 | 
| zero_val | 
168506 | 
1 | 
 | 
 | 
T1 | 
2328 | 
 | 
T2 | 
370 | 
 | 
T3 | 
4 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
18 | 
0 | 
18 | 
100.00 | 
 | 
Automatically Generated Cross Bins for entropy_timer_cross
Bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
higher_val | 
auto[0] | 
43158 | 
1 | 
 | 
 | 
T32 | 
7 | 
 | 
T7 | 
20 | 
 | 
T33 | 
101 | 
| higher_val | 
higher_val | 
auto[1] | 
20872 | 
1 | 
 | 
 | 
T1 | 
286 | 
 | 
T2 | 
46 | 
 | 
T36 | 
281 | 
| higher_val | 
lower_val | 
auto[0] | 
43539 | 
1 | 
 | 
 | 
T32 | 
9 | 
 | 
T7 | 
28 | 
 | 
T33 | 
101 | 
| higher_val | 
lower_val | 
auto[1] | 
20873 | 
1 | 
 | 
 | 
T1 | 
270 | 
 | 
T2 | 
43 | 
 | 
T36 | 
262 | 
| higher_val | 
zero_val | 
auto[0] | 
77 | 
1 | 
 | 
 | 
T38 | 
1 | 
 | 
T48 | 
1 | 
 | 
T43 | 
1 | 
| higher_val | 
zero_val | 
auto[1] | 
42207 | 
1 | 
 | 
 | 
T1 | 
586 | 
 | 
T2 | 
94 | 
 | 
T3 | 
1 | 
| lower_val | 
higher_val | 
auto[0] | 
42443 | 
1 | 
 | 
 | 
T32 | 
3 | 
 | 
T7 | 
17 | 
 | 
T33 | 
94 | 
| lower_val | 
higher_val | 
auto[1] | 
21205 | 
1 | 
 | 
 | 
T1 | 
238 | 
 | 
T2 | 
58 | 
 | 
T3 | 
1 | 
| lower_val | 
lower_val | 
auto[0] | 
42597 | 
1 | 
 | 
 | 
T32 | 
7 | 
 | 
T7 | 
21 | 
 | 
T33 | 
94 | 
| lower_val | 
lower_val | 
auto[1] | 
20913 | 
1 | 
 | 
 | 
T1 | 
252 | 
 | 
T2 | 
48 | 
 | 
T36 | 
287 | 
| lower_val | 
zero_val | 
auto[0] | 
67 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T45 | 
1 | 
 | 
T20 | 
1 | 
| lower_val | 
zero_val | 
auto[1] | 
41435 | 
1 | 
 | 
 | 
T1 | 
557 | 
 | 
T2 | 
82 | 
 | 
T3 | 
3 | 
| zero_val | 
higher_val | 
auto[0] | 
508 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 | 
T7 | 
1 | 
| zero_val | 
higher_val | 
auto[1] | 
109 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T2 | 
1 | 
 | 
T36 | 
3 | 
| zero_val | 
lower_val | 
auto[0] | 
531 | 
1 | 
 | 
 | 
T32 | 
1 | 
 | 
T33 | 
1 | 
 | 
T37 | 
1 | 
| zero_val | 
lower_val | 
auto[1] | 
115 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
2 | 
 | 
T98 | 
1 | 
| zero_val | 
zero_val | 
auto[0] | 
249 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T36 | 
1 | 
 | 
T38 | 
1 | 
| zero_val | 
zero_val | 
auto[1] | 
175 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T36 | 
5 |