Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98897404	1			T1	461652		T2	209558		T3	370
all_pins[1]	98897404	1			T1	461652		T2	209558		T3	370
all_pins[2]	98897404	1			T1	461652		T2	209558		T3	370

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295883002	1			T1	138159		T2	628112		T3	1109
values[0x1]	809210	1			T1	3364		T2	562		T3	1
transitions[0x0=>0x1]	807147	1			T1	3364		T2	562		T3	1
transitions[0x1=>0x0]	807161	1			T1	3364		T2	562		T3	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98396992	1			T1	458288		T2	208996		T3	369
all_pins[0]	values[0x1]	500412	1			T1	3364		T2	562		T3	1
all_pins[0]	transitions[0x0=>0x1]	500395	1			T1	3364		T2	562		T3	1
all_pins[0]	transitions[0x1=>0x0]	5850	1			T45	9		T8	30		T47	2
all_pins[1]	values[0x0]	98891537	1			T1	461652		T2	209558		T3	370
all_pins[1]	values[0x1]	5867	1			T45	9		T8	30		T47	2
all_pins[1]	transitions[0x0=>0x1]	5647	1			T45	9		T8	30		T47	2
all_pins[1]	transitions[0x1=>0x0]	302711	1			T20	631		T44	708		T76	1237
all_pins[2]	values[0x0]	98594473	1			T1	461652		T2	209558		T3	370
all_pins[2]	values[0x1]	302931	1			T20	631		T44	708		T76	1237
all_pins[2]	transitions[0x0=>0x1]	301105	1			T20	631		T44	708		T76	1236
all_pins[2]	transitions[0x1=>0x0]	498600	1			T1	3364		T2	562		T3	1